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128K
X25138
16K x 8 Bit
5MHz SPI Serial E2PROM with Block LockTM Protection
FEATURES DESCRIPTION The X25138 is a CMOS 128K-bit serial E2PROM, internally organized as 16K x 8. The X25138 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25138 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25138 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25138 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25138 utilizes Xicor's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years.
* * * * * * * *
* *
*
5MHz Clock Rate Low Power CMOS <1mA Standby Current <5mA Active Current 2.5V To 5.5V Power Supply SPI Modes (0,0 & 1,1) 16K X 8 Bits 32 Byte Page Mode Block LockTM Protection Protect 1/4, 1/2 or all of E2PROM Array Programmable Hardware Write Protection In-Circuit Programmable ROM Mode Built-in Inadvertent Write Protection Power-Up/Down protection circuitry Write Enable Latch Write Protect Pin Self-Timed Write Cycle 5ms Write Cycle Time (Typical) High Reliability Endurance: 100,000 cycles Data Retention: 100 Years ESD protection: 2000V on all pins Packages 8-Lead XBGA 8, 14-Lead SOIC 8-Lead PDIP 8-Lead TSSOP
FUNCTIONAL DIAGRAM
ST ATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 128 128 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 128 128 X 256 16K BYTE ARRAY
256 256 X 256
WP
WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE
Direct WriteO and Block LockO Protection is a trademark of Xicor, Inc.
OXicor, Inc. 1998 Patents Pending 7056-1.5 8/13/98 T2/C0/D1 EW 1
DATA REGISTER
7037 FRM F01
Characteristics subject to change without notice
X25138
PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25138 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25138 will be in the standby power mode. CS LOW enables the X25138, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is "1", nonvolatile writes to the X25138 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the PIN NAMES Symbol CS
SO SI SCK
X25138 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is "0". This allows the user to install the X25138 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set "1". Hold (HOLD) HOLD is used in conjunction with the CS pin to pause the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause
PIN CONFIGURATION
8-LEAD TSSOP HOLD Vcc CS SO 1 2 3 4 8 7 6 5 SCK SI Vss .114" WP
X25138
.252 in.
8-Lead XBGA: Top View
.078"
HOLD 1 VCC 2 SI
8
S0
.238"
7 CS 6 VSS 5
WP
3
SCK 4
14 Lead SOIC CS SO NC 1 2 3 4 5 6 7 .228" X25138 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI
Description
Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect
7037 FRM T01
.336"
NC NC WP VSS
WP
VSS VCC
8 Lead PDIP/SOIC CS SO WP VSS 1 2 3 4 X25138 8 7 6 5 VCC HOLD SCK SI
HOLD
NC
3091 FM 03
2
X25138
the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PRINCIPLES OF OPERATION The X25138 is a 16K x 8 E2PROM designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular microcontroller families. The X25138 contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising SCK. CS must be LOW and the HOLD and WP inputs must be HIGH during the entire operation. Table 1 contains a list of the instructions and their opcodes. All instructions, addresses and data are transferred MSB first. Data input is sampled on the first rising edge of SCK after CS goes LOW. SCK is static, allowing the user to stop the clock and then resume operations. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input to place the X25138 into a "PAUSE" condition. After releasing HOLD, the X25138 will resume operation from the point when HOLD was first asserted. Write Enable Latch The X25138 contains a "write enable" latch. This latch must be SET before a write operation will be completed internally. The WREN instruction will set the latch and the WRDI instruction will reset the latch. This latch is automatically reset upon a power-up condition and after the completion of a byte, page, or status register write cycle. Table 1. Instruction Set Instruction Name
WREN WRDI RDSR WRSR READ WRITE
Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows:
7 WPEN 6 X 5 X 4 X 3 BL1 2 BL0 1 WEL 0 WIP
7037 FRM T02
WPEN, BL0 and BL1 are set by the WRSR instruction. WEL and WIP are read-only and automatically set by other operations. The Write-In-Process (WIP) bit indicates whether the X25138 is busy with a write operation. When set to a "1", a write is in progress, when set to a "0", no write is in progress. During a write, all other bits are set to "1". The Write Enable Latch (WEL) bit indicates the status of the "write enable" latch. When set to a "1", the latch is set, when set to a "0", the latch is reset. The Block Lock (BL0 and BL1) bits are nonvolatile and allow the user to select one of four levels of protection. The X25138 is divided into four 32K-bit segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated below. Status Register Bits BL1
0 0 1 1
BL0
0 1 0 1
Array Addresses Protected
None $3000-$3FFF $2000-$3FFF $0000-$3FFF
7037 FRM T03
Instruction Format*
0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations) Reset the Write Enable Latch (Disable Write Operations) Read Status Register Write Status Register Read Data from Memory Array beginning at selected address Write Data to Memory Array beginning at Selected Address (1 to 32 Bytes)
7037 FRM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25138
The Write-Protect-Enable (WPEN) bit is available for the X25138 as a nonvolatile enable bit for the WP pin.
WPEN WP WEL Protected Unprotected Status Blocks Blocks Register
0 0 1 1 X X
X X LOW LOW HIGH HIGH
0 1 0 1 0 1
Protected Protected Protected Protected Protected Protected
Protected Writable Protected Writable Protected Writable
Protected Writable Protected Protected Protected Writable
7037 FRM T05
at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached ($3FFF) the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS HIGH. Refer to the read E2PROM array operation sequence illustrated in Figure 1. To read the status register the CS line is first pulled LOW to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Figure 2 illustrates the read status register sequence. Write Sequence Prior to any attempt to write data into the X25138, the "write enable" latch must first be set by issuing the WREN instruction (See Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the X25138. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the E2PROM memory array, the user issues the WRITE instruction, followed by the address and then the data to be written. This is minimally a thirty-two clock operation. CS must go LOW and remain LOW for the duration of the operation. The host may continue to write up to 32 bytes of data to the X25138. The only restriction is the 32 bytes must reside on the same page. If the address counter reaches the end of the page and the clock continues, the counter will "roll over" to the first address of the page and overwrite any data that may have been written. For the write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of data byte N is clocked in. If it is brought HIGH at any other time the write operation will not be completed. Refer to Figures 4 and 5 below for a detailed illustration of the write sequences and time frames in which CS going HIGH are valid. To write to the status register, the WRSR instruction is followed by the data to be written. Data bits 0, 1, 4, 5 and 6 must be "0". Figure 6 illustrates this sequence. While the write is in progress following a status register or E2PROM write sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be HIGH.
4
Programmable Hardware Write Protection The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the Programmable Hardware Write Protect feature. Hardware Write Protection is enabled when WP pin is LOW, and the WPEN bit is "1". Hardware Write Protection is disabled when either the WP pin is HIGH or the WPEN bit is "0". When the chip is hardware write protected, nonvolatile writes are disabled to the Status Register, including the Block Lock bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written. In Circuit Programmable ROM Mode Note that since the WPEN bit is write protected, it cannot be changed back to a LOW state; so write protection is enabled as long as the WP pin is held LOW. Thus an In Circuit Programmable ROM function can be emplemented by hardwiring the WP pin to Vss, writing to and Block Locking the desired portion of the array to be ROM, and then programming the WPEN bit HIGH. The table above defines the program protect status for each combination of WPEN and WP. Clock and Data Timing Data input on the SI line is latched on the rising edge of SCK. Data is output on the SO line by the falling edge of SCK. Read Sequence When reading from the E2PROM memory array, CS is first pulled LOW to select the device. The 8-bit READ instruction is transmitted to the X25138, followed by the 16-bit address of which the last 14 are used. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory
X25138
Hold Operation The HOLD input should be HIGH (at VIH) under normal operation. If a data transfer is to be interrupted HOLD can be pulled LOW to suspend the transfer until it can be resumed. The only restriction is the SCK input must be LOW when HOLD is first pulled LOW and SCK must also be LOW when HOLD is released. The HOLD input may be tied HIGH either directly to VCC or tied to VCC through a resistor. Operational Notes The X25138 powers-up in the following state: * The device is in the low power standby state. * A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. * SO pin is high impedance. * The "write enable" latch is reset. Data Protection The following circuitry has been included to prevent inadvertent writes: * The "write enable" latch is reset upon power-up. * A WREN instruction must be issued to set the "write enable" latch. * CS must come HIGH at the proper clock count in order to start a write cycle.
Figure 1. Read E2PROM Array Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION SI
16 BIT ADDRESS 15 14 13 3 2 1 0
HIGH IMPEDANCE SO
DATA OUT 7 MSB 6 5 4 3 2 1 0
7037 FRM F03
Figure 2. Read Status Register Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14
INSTRUCTION SI
DATA OUT HIGH IMPEDANCE SO 7 MSB 6 5 4 3 2 1 0
7037 FRM F04
5
X25138
Figure 3. Write Enable Latch Sequence
CS
0 SCK
1
2
3
4
5
6
7
SI
SO
HIGH IMPEDANCE
7037 FRM F05
Figure 4. Byte Write Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION SI
16 BIT ADDRESS 15 14 13 3 2 1 0 7 6 5
DATA BYTE 4 3 2 1 0
HIGH IMPEDANCE SO
7037 FRM F06
6
X25138
Figure 5. Page Write Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
INSTRUCTION SI
16 BIT ADDRESS 15 14 13 3 2 1 0 7 6 5
DATA BYTE 1 4 3 2 1 0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK
DATA BYTE 2 SI 7 6 5 4 3 2 1 0 7 6
DATA BYTE 3 5 4 3 2 1 0 6
DATA BYTE N 5 4 3 2 1 0
7037 FRM F07
Figure 6. Write Status Register Operation Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
INSTRUCTION SI 7 6 5
DATA BYTE 4 3 2 1 0
SO
HIGH IMPEDANCE
7037 FRM F08
7
X25138
ABSOLUTE MAXIMUM RATINGS* Temperature under Bias....................-65C to +135C Storage Temperature ........................-65C to +150C Voltage on any Pin with Respect to VSS .........................................................-1V to +7V D.C. Output Current ............................................. 5mA (Soldering, 10 seconds) ..............................300C RECOMMENDED OPERATING CONDITIONS Temperature
Commercial Industrial Military
*COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage
X25138 X25138-2.5
Min.
0C -40C -55C
Max.
+70C +85C +125C
7037 FRM T06
Limits
5V 10% 2.5V to 5.5V
7037 FRM T07
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol
ICC ISB ILI ILO VIL(1) VIH
(1)
Parameter
VCC Supply Current (Active) VCC Supply Current (Standby) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage
Limits Min. Max.
5 1 10 10 -1 VCC x 0.7 VCC-0.8 0.4 VCC-0.3 VCC x 0.3 VCC + 0.5 0.4
Units
mA mA mA mA V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 5MHz,
CS = VCC, VIN = VSS or VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC
VOL1 VOH1 VOL2 VOH2
IOL = 3mA, VCC = 5V IOH = -1.6mA, VCC = 5V IOL = 1.5mA, VCC = 3V IOH = -0.4mA, VCC = 3V
7037 FRM T08 POWER-UP TIMING
Symbol
TPUR(3) TPUW
(3)
Parameter
Power-up to Read Operation Power-up to Write Operation
Min.
Max.
1 1
Units
ms ms
7037 FRM T09
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
CI/O(3) CIN
(3)
Parameter
Output Capacitance (SO) Input Capacitance (SCK, SI, CS, WP, HOLD)
Max.
8 6
Units
pF pF
Test Conditions
VI/O = 0V VIN = 0V
7037 FRM T10
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are periodically sampled and not 100% tested.
8
X25138
EQUIVALENT A.C. LOAD CIRCUIT
5V 1.44KW OUTPUT 1.95KW 1.64KW OUTPUT 4.63KW 3V
A.C. CONDITIONS OF TEST
Input Pulse Levels Input Rise and Fall Times Input and OutputTiming Levels
100pF
VCC x 0.1 to VCC x 0.9 10ns VCC X 0.5
7037 FRM T11
100pF
7037 FRM F09
A.C. OPERATING CHARACTERISTICS Data Input Timing VCC = 2.5V-5.5V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(4) tFI(4) tHD tCD tCS tWC
(5)
VCC = 4.5V-5.5V Min.
0 200 100 100 80 80 20 20
Parameter
Clock Frequency Cycle Time CS Lead Time CS Lag Time Clock HIGH Time Clock LOW Time Data Setup Time Data Hold Time Data In Rise Time Data In Fall Time
Min.
0 300 150 150 130 130 30 30
Max.
3.3
Max.
5
Units
MHz ns ns ns ns ns ns ns
2 2 60 60 100 10 40 40 100
2 2
ms ms ns ns ns
HOLD Setup Time HOLD Hold Time CS Deselect Time
Write Cycle Time
10
ms
7037 FRM T12
Data Output Timing VCC = 2.5V-5.5V Symbol
fSCK tDIS tV tHO tRO tLZ
(4)
VCC = 4.5V-5.5V Min.
0
Parameter
Clock Frequency Output Disable Time Output Valid from Clock LOW Output Hold Time Output Rise Time Output Fall Time
Min.
0
Max.
3.3 150 130
Max.
5 100 80
Units
MHz ns ns ns ns ns ns ns
7037 FRM T13
0 50 50 50 50
0 50 50 50 50
tFO(4)
(4) (4)
tHZ
HOLD HIGH to Output in Low Z HOLD LOW to Output in High Z
Notes: (4) This parameter is periodically sampled and not 100% tested. (5) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle
9
X25138
Serial Output Timing
CS tCYC SCK tV SO MSB OUT MSB-1 OUT t HO tWL LSB OUT tDIS tWH tLAG
SI
ADDR LSB IN
7037 FRM F10
Serial Input Timing
t CS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
HIGH IMPEDANCE SO
7037 FRM F11
10
X25138
Hold Timing
CS tHD SCK tHZ SO tLZ tCD tHD tCD
SI
HOLD
7037 FRM F12
11
X25138
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) PIN 1 INDEX PIN 1 0.300 (7.62) REF. 0.060 (1.52) 0.020 (0.51)
HALF SHOULDER WIDTH ON ALL END PINS OPTIONAL SEATING PLANE 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25)
0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
0.015 (0.38) MAX.
0.325 (8.25) 0.300 (7.62)
TYP .0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X25138
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.019 (0.49)
0.188 (4.78) 0.197 (5.00)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.19) 0.010 (0.25)
0.010 (0.25) 0.020 (0.50) X 45
0.050" TYPICAL
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" TYPICAL
FOOTPRINT
0.030" TYPICAL 8 PLACES
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25138
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80) 0.158 (4.00) PIN 1 INDEX
0.228 (5.80) 0.244 (6.20)
PIN 1
0.014 (0.35) 0.020 (0.51) 0.336 (8.55) 0.345 (8.75)
(4X) 7
0.053 (1.35) 0.069 (1.75)
0.050 (1.27)
0.004 (0.10) 0.010 (0.25)
0.050" T ypical
0.010 (0.25) X 45 0.020 (0.50)
0.050" Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937)
0.250"
FOOTPRINT
0.030"Typical 14 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X25138
8-LEAD PLASTIC, TSSOP PACKAGE TYPE V ,
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.114 (2.9) .122 (3.1)
.047 (1.20)
.0075 (.19) .0118 (.30)
.002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05)
See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
15
X25138
PACKAGING INFORMATION
8-Lead XBGA
8-Lead XBGA Complete Part Number X25138Z-2.5 X25138ZI-2.5
8-Lead XBGA: Top View
.078"
Top Mark XAAD XACR
X25138: Bottom View
21530
HOLD 1 VCC 2 SI
8
S0
.238"
7 CS 6 VSS 5
WP
3
SCK 4
50020
S0
HOLD PIN 1 35020
CS
VCC
604630
VSS 100030
SI
WP
SCK
120030
198230
43050
183330
21530
35020
ALL DIMENSIONS IN mM ALL DIMENSIONS ARE TYPICAL VALUES
16
604630
X25138
ORDERING INFORMATION X25138 Device P T -V V CC Limits Blank = 4.5V to 5.5V 2.5 = 2.5 to 5.5V Temperature Range Blank = Commercial = 0C to +70C I = Industrial = -40C to +85C
Package S8 = 8-Lead SOIC S14 = 14-Lead SOIC V8 = 8-Lead TSSOP P = 8-Lead DIP Z = 8-Lead XBGA PART MARK CONVENTION 8-Lead TSSOP EYWW 5138XX AA = 4.5 to 5.5V, -20 to +85C AC = 2.5 to 5.5V, -20 to +85C F = 2.5 to 5.5V, 0 to +70C G = 2.5 to 5.5V, -40 to +85C Blank = 4.5 to 5.5V, 0 to +70C I = 4.5 to 5.5V, -40 to +85C
LIMITED WARRANTY Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence. Xicor's products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
8-Lead SOIC/PDIP X5138 X XX Blank = 8-Lead SOIC P = 8-Lead PDIP
8-Lead XBGA Complete Part Number X25138Z-2.5 X25138ZI-2.5
Top Mark XAAD XACR
AA = 4.5 to 5.5V, -20 to +85C AC = 2.5 to 5.5V, -20 to +85C F = 2.5 to 5.5V, 0 to +70C G = 2.5 to 5.5V, -40 to +85C Blank = 4.5 to 5.5V, 0 to +70C I = 4.5 to 5.5V, -40 to +85C
17
X25138
U.S. SALES OFFICES
Corporate Office Xicor Inc. 1511 Buckeye Drive Milpitas, CA 95035 Phone: 408/432-8888 Fax: 408/432-0640 E-mail: info@xicor.com Southeast Region Xicor Inc. 100 E. Sybelia Ave. Suite 355 Maitland, FL 32751 Phone: 407/740-8282 Fax: 407/740-8602 E-mail: xicor-se@xicor.com Mid-Atlantic Region Xicor Inc. 50 North Street Danbury, CT 06810 Phone: 203/743-1701 Fax: 203/794-9501 E-mail: xicor-ma@xicor.com North Central Region Xicor Inc. 810 South Bartlett Road Suite 103 Streamwood, IL 60107 Phone: 630/372-3200 Fax: 630/372-3210 E-mail: xicor-nc@xicor.com South Central Region Xicor Inc. 11884 Greenville Ave. Suite 102 Dallas, TX 75243 Phone: 972/669-2022 Fax: 972/644-5835 E-mail: xicor-sc@xicor.com Southwest Region Xicor Inc. 4100 Newport Place Drive Suite 710 Newport Beach, CA 92660 Phone: 714/752-8700 Fax: 714/752-8634 E-mail: xicor-sw@xicor.com Northwest Region Xicor Inc. 3333 Bowers Ave. Suite 238 Santa Clara, CA 95054 Phone: 408/492-1966 Fax: 408/980-9478 E-mail: xicor-nw@xicor.com
INTERNATIONAL SALES OFFICES
EUROPE Northern Europe Xicor Ltd. Grant Thornton House Witan Way Witney Oxford OX8 6FE UK Phone: (44) 1933.700544 Fax: (44) 1933.700533 E-mail: xicor-uk@xicor.com Central Europe Xicor GmbH Technopark Neukeferloh Bretonischer Ring 15 85630 Grasbrunn bei Muenchen Germany Phone: (49) 8946.10080 Fax: (49) 8946.05472 E-mail: xicor-gm@xicor.com ASIA/PACIFIC Japan Xicor Japan K.K. Suzuki Building, 4th Floor 1-6-8 Shinjuku, Shinjuku-ku Tokyo 160, Japan Phone: (81) 3322.52004 Fax: (81) 3322.52319 E-mail: xicor-jp@xicor.com Mainland China Taiwan/Hong Kong Xicor Hong Kong, Ltd. Room 7, Business Centre B1, Grand Stanford Harbour View 70 Mody Road, Tsimshatsui East Kowloon, Hong Kong Phone: (852) 2313 7607 Fax: (852) 2313 7507 E-mail: xicor_hongkong@xicor.com Singapore/Malaysia/India Xicor Inc. 3333 Bowers Ave. Suite 238 Santa Clara, CA 95054 Phone: 408/492-1966 Fax: 408/980-9478 E-mail: xicor-nw@xicor.com Korea Xicor Korea, Ltd. 27th Fl., Korea World Trade Ctr. 159, Samsung-dong Kangnam Ku Seoul 135-729 Korea Phone: (82) 2.551.2750 Fax: (82) 2.551.2710 E-mail: xicor-ka@xicor.com ( ) = Country Code
Xicor product information is available at:
www.xicor.com
18 Xicor, Inc., Marketing Dept. 1511 Buckeye Drive, Milpitas, California 95035-7493 TEL 408/432-8888 FAX 408/432-0640

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